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d a t a sh eet product speci?cation file under integrated circuits, ic20 1997 dec 15 integrated circuits p83c524; p80c528; p83c528 8-bit microcontrollers
1997 dec 15 2 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 functional diagram 7 pinning information 7.1 pinning 7.2 pin description 8 functional description 8.1 general 8.2 instruction set execution 9 memory organization 9.1 program memory 9.2 internal data memory 9.3 addressing 10 i/o facilities 11 timers/counters 11.1 timer 0 and timer 1 11.1.1 timer/counter mode control register (tmod) 11.1.2 timer/counter control register (tcon) 11.2 timer 2 11.2.1 timer 2 control register (t2con) 11.2.2 capture mode 11.2.3 automatic reload mode 11.2.4 baud rate generator mode 11.3 watchdog timer t3 12 serial port (uart) 12.1 serial port control register (scon) 12.2 sm0 and sm1 operating modes (scon) 13 bit-level i 2 c interface 13.1 i 2 c interrupt register (s1int) 13.2 single-bit data register with i 2 c auto-clock (s1bit) 13.2.1 reading or writing the s1bit sfr 13.3 control and status register for the i 2 c-bus (s1scs) 14 interrupt system 14.1 interrupt enable register (ie) 14.2 interrupt priority register (ip) 14.3 interrupt vectors 15 idle and power-down operation 15.1 power control register (pcon) 15.2 idle mode 15.3 power-down mode 15.4 wake-up from power-down mode 16 oscillator circuit 17 reset circuit 17.1 power-on reset 18 instruction set 19 limiting values 20 dc characteristics 21 ac characteristics 21.1 ac characteristics 16 mhz version 21.2 ac characteristics 24 mhz version 22 i 2 c characteristics (bit-level) 23 xtal1 characteristics 24 serial port characteristics 25 timing diagrams 25.1 timing symbol definitions 26 package outlines 27 soldering 27.1 introduction 27.2 dip 27.2.1 soldering by dipping or by wave 27.2.2 repairing soldered joints 27.3 plcc and qfp 27.3.1 reflow soldering 27.3.2 wave soldering 27.3.3 repairing soldered joints 28 definitions 29 life support applications 30 purchase of philips i 2 c components
1997 dec 15 3 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 1 features 80c51 cpu 32 kbytes on-chip rom, expandable externally to 64 kbytes program memory address space p83c524: C 16 kbytes on-chip rom, expandable externally from 32 kbytes to 64 kbytes program memory address space (address space 16 k to 32 k not usable) p80c528: C romless version of p83c528 p83c528: C 32 kbytes on-chip rom, expandable externally from 32 kbytes to 64 kbytes program memory address space eprom versions are available: see separate data sheet p87c524 and p87c528 512 bytes on-chip ram, expandable externally to 64 kbytes data memory address space four 8-bit i/o ports full-duplex uart compatible with the standard 80c51 and the 8052 two standard 16-bit timer/counters an additional 16-bit timer (functionally equivalent to the timer 2 of the 8052) on-chip watchdog timer (wdt) with an own oscillator bit-level i 2 c-bus hardware serial i/o port 7-source and 7-vector interrupt structure with 2 priority levels up to 3 external interrupt request inputs two programmable power reduction modes (idle and power-down) termination of idle mode by any interrupt, external or wdt (watchdog) reset wake-up from power-down by external interrupt, external or wdt reset rom code protection xtal frequency range: 3.5 mhz to 16 mhz and 3.5 mhz to 24 mhz all packaging pin-outs fully compatible to the standard 8051/8052. 2 general description the p83c524 and p83c528 single-chip 8-bit microcontrollers are manufactured in an advanced cmos process and are derivatives of the pcb80c51 microcontroller family. these devices provide architectural enhancements that make them applicable in a variety of applications in general control systems, especially in those systems which need a large rom and ram capacity on chip. the p83c524 and p83c528 contain a non-volatile 16 k 8 respectively 32 k 8 read-only program memory, a volatile 512 bytes 8 read/write data memory, four 8-bit i/o ports, two 16-bit timer/event counters (identical to the timers of the 80c51), a 16-bit timer (identical to the timer 2 of the 8052), a multi-source, two-priority-level, nested interrupt structure, two serial interfaces (uart and bit-level i 2 c-bus), a watchdog timer (wdt) with a separate oscillator, an on-chip oscillator and timing circuits. for systems that require extra capability, the p83c524 and p83c528 can be expanded using standard ttl compatible memories and logic. the device also functions as an arithmetic processor having facilities for both binary and bcd arithmetic plus bit-handling capabilities. the p83c524 and p83c528 have the same instruction set as the pcb80c51 which consists of over 100 instructions: 49 one-byte, 46 two-byte and 16 three-byte. with a 16 mhz crystal, 58% of the instructions are executed in 750 ns and 40% in 1.5 m s. multiply and divide instructions require 3 m s.
1997 dec 15 4 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 3 quick reference data 4 ordering information symbol parameter condition min. max. unit p83c524, p80c528, p83c528 (see characteristics tables for extended temperature range versions) v dd supply voltage range 4.5 5.5 v i dd supply current: operating modes 16 mhz v dd = 5.5 v, f clk = 16 mhz - 33 ma i id supply current: idle mode 16 mhz v dd = 5.5 v, f clk = 16 mhz - 6ma i pd supply current: power-down mode 2v v pd v dd max. - 100 m a p tot total power dissipation - 1w t stg storage temperature range - 65 +150 c t amb operating ambient temperature range - 40 +85 c extended type number package temperature range ( c) freq. (mhz) name description version romless p80c528ebp dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 3.5 to 16 p80c528efp - 40 to +85 p80c528ibp 0 to +70 3.5 to 24 p80c528ifp - 40 to +85 p80c528eba plcc44 plastic leaded chip carrier; 44 leads sot187-2 0 to +70 3.5 to 16 p80c528efa - 40 to +85 p80c528iba 0 to +70 3.5 to 24 p80c528ifa - 40 to +85 p80c528ebb qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 0 to +70 3.5 to 16 p80c528efb - 40 to +85 p80c528ibb 0 to +70 3.5 to 24 p80c528ifb - 40 to +85 rom p83c524ebp dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 3.5 to 16 p83c524efp - 40 to +85 p83c524ibp 0 to +70 3.5 to 24 p83c524ifp - 40 to +85 p83c524eba plcc44 plastic leaded chip carrier; 44 leads sot187-2 0 to +70 3.5 to 16 p83c524efa - 40 to +85 p83c524iba 0 to +70 3.5 to 24 p83c524ifa - 40 to +85 p83c524ebb qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 0 to +70 3.5 to 16 p83c524efb - 40 to +85 p83c524ibb 0 to +70 3.5 to 24 p83c524ifb - 40 to +85
1997 dec 15 5 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 p83c528ebp dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 3.5 to 16 p83c528efp - 40 to +85 p83c528ibp 0 to +70 3.5 to 24 p83c528ifp - 40 to +85 P83C528EBA plcc44 plastic leaded chip carrier; 44 leads sot187-2 0 to +70 3.5 to 16 p83c528efa - 40 to +85 p83c528iba 0 to +70 3.5 to 24 p83c528ifa - 40 to +85 p83c528ebb qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 0 to +70 3.5 to 16 p83c528efb - 40 to +85 p83c528ibb 0 to +70 3.5 to 24 p83c528ifb - 40 to +85 extended type number package temperature range ( c) freq. (mhz) name description version
1997 dec 15 6 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 5 block diagram handbook, full pagewidth programmable i/o 64k-byte bus expansion control oscillator and timing cpu internal interrupts program memory (32 k x 8 rom/ eprom) data memory (256 x 8 ram) programmable serial port full duplex uart synchronous shift two 16-bit timer/event counters xtal2 xtal1 frequency reference t0 t1 counters external interrupts control parallel ports, address/data bus and i/o pins serial in serial out int1 int0 mbc455 data memory (256 x 8 ram) 16-bit timer watchdog timer t2 t2ex rst bit-level interface i c 2 aux - ram ram shared with port 3 sda scl fig.1 block diagram. program memory (32 k x 8 rom or 16 k x 8 rom) p83c524 p80c528 p83c528
1997 dec 15 7 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 6 functional diagram fig.2 functional diagram. handbook, full pagewidth port 0 address and data bus address bus port 1 port 2 scl sda rst xtal1 xtal2 ale ea psen port 3 rxd / data txd / clock t0 t1 int0 int1 wr rd alternative functions p83c528 mbc454 - 1 t2 t2ex v dd v ss p83c524 p80c528 p83c528
1997 dec 15 8 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 7 pinning information 7.1 pinning fig.3 pin configuration dip40 (sot129-1). handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 t2 p1.0 t2ex p1.1 p1.2 p1.3 p1.4 p1.5 scl p1.6 sda p1.7 rst rxd / data p3.0 txd / clock p3.1 t0 p3.4 t1 p3.5 xtal2 xtal1 v ss v dd p0.0 ad0 p0.1 ad1 p0.2 ad2 p0.3 ad3 p0.4 ad4 p0.5 ad5 p0.6 ad6 p0.7 ad7 ale p2.7 a15 p2.6 a14 p2.5 a13 p2.4 a12 p2.3 a11 p2.2 a10 p2.1 a9 p2.0 a8 p83c528 int0 p3.2 int1 p3.3 wr p3.6 rd p3.7 psen mbc453 ea p83c524 p80c528 p83c528
1997 dec 15 9 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.4 pin configuration qfp44 (sot307-2). handbook, full pagewidth 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 p1.4 p1.3 p1.2 p1.1 / t2ex p1.0 / t2 n.c. v dd p0.0 / ad0 p0.1 / ad1 p0.2 / ad2 p0.3 / ad3 p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 n.c. ale p2.7 / a15 p2.6 / a14 p2.5 / a13 ea psen p1.5 scl / p1.6 sda / p1.7 rst rxd / data / p3.0 n.c. txd / clock / p3.1 t0 / p3.4 t1 / p3.5 int0 / p3.2 int1 / p3.3 xtal2 xtal1 v ss n.c. p2.0 / a8 p2.1 / a9 p2.2 / a10 p2.3 / a11 p2.4 / a12 wr / p3.6 rd / p3.7 p83c528 mbc452 1 2 8 7 6 5 4 3 9 10 11 12 14 15 16 17 18 19 13 20 21 22 27 26 25 24 23 28 29 30 31 32 33 35 34 36 37 38 39 40 41 42 43 44 p83c524 p80c528 p83c528
1997 dec 15 10 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.5 pin configuration plcc44 (sot187-2). handbook, full pagewidth 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 p1.4 p1.3 p1.2 p1.1 / t2ex p1.0 / t2 n.c. v dd p0.0 / ad0 p0.1 / ad1 p0.2 / ad2 p0.3 / ad3 p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 n.c. ale p2.7 / a15 p2.6 / a14 p2.5 / a13 ea psen p1.5 scl / p1.6 sda / p1.7 rst rxd / data / p3.0 n.c. txd / clock / p3.1 t0 / p3.4 t1 / p3.5 int0 / p3.2 int1 / p3.3 xtal2 xtal1 v ss n.c. p2.0 / a8 p2.1 / a9 p2.2 / a10 p2.3 / a11 p2.4 / a12 wr / p3.6 rd / p3.7 p83c528 mbc452 p83c524 p80c528 p83c528
1997 dec 15 11 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 7.2 pin description table 1 pin description for p83c524, p80c528 and p83c528; see note 1 symbol pin description sot 129-1 sot 187-2 sot 307-2 p1.0 - p1.7 1 to 8 2 - 9 (1 n.c.) 1 - 3, 40 - 44 (39 n.c.) port 1 : 8-bit quasi-bidirectional i/o port. port 1 can sink/source one ttl (= 4 lsttl) input. it can drive cmos inputs without external pull-ups, except p1.6 and p1.7 which have open drain outputs. port 1 alternative functions: t21240 p1.0 timer/event counter 2 external event counter input (falling edge triggered) t2ex 2 3 41 p1.1 timer/event counter 2 capture/reload trigger or external interrupt 2 input (falling edge triggered) scl 7 8 2 p1.6 i 2 c-bus serial port clock line sda 8 9 3 p1.7 i 2 c-bus serial port data line. rst 9 10 4 reset : a high level on this pin for two machine cycles while the oscillator is running, resets the device. an internal pull-down resistor permits power-on reset using only a capacitor connected to v dd . after a wdt over?ow this pin is pulled high while the internal reset signal is active. p3.0 - p3.7 10 - 17 11, 13 - 19 (12 n.c.) 5, 7 - 13 (6 n.c.) port 3 : 8-bit quasi-bidirectional i/o port with internal pull-ups. port 3 can sink/source one ttl (= 4 lsttl) input. it can drive cmos inputs without external pull-ups. port 3 alternative functions: rxd/data 10 11 5 p3.0 serial port data input (asynchronous) or data input/output (synchronous) txd/clock 11 13 7 p3.1 serial port data output (asynchronous) or clock output (synchronous) int0 12 14 8 p3.2 external interrupt 0 or gate control input for timer/event counter 0 int1 13 15 9 p3.3 external interrupt 1 or gate control input for timer/event counter 1 t0 14 16 10 p3.4 external input for timer/event counter 0 t1 15 17 11 p3.5 external input for timer/event counter 1 wr 16 18 12 p3.6 external data memory write strobe rd 17 19 13 p3.7 external data memory read strobe. the generation or use of a port 3 pin as an alternative function is carried out automatically by the p83c528 provided the associated special function register (sfr) bit is set high. xtal2 18 20 14 crystal input 2 : output of the inverting ampli?er that forms the oscillator. this pin left open-circuit when an external oscillator clock is used (see figures 22 and 23).
1997 dec 15 12 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 note 1. to avoid a 'latch-up' effect at power-on, the voltage on any pin (at any time) must not be higher than v dd +0.5 v or lower than v ss - 0.5 v respectively. xtal1 19 21 15 crystal input 1 : input to the inverting ampli?er that forms the oscillator, and input to the internal clock generator. receives the external oscillator clock signal when an external oscillator is used (see figures 22 and 23). v ss 20 22 16 ground : circuit ground potential. p2.0-p2.7 21 - 28 24 - 31 (23 n.c.) 18 - 25 (17 n.c.) port 2 : 8-bit quasi-bidirectional i/o port with internal pull-ups. during access to external memories (ram/rom) that use 16-bit addresses (movx @dptr) port 2 emits the high-order address byte (a8 to a15). port 2 can sink/source one ttl (= 4 lsttl) input. it can drive cmos inputs without external pull-ups. psen 29 32 26 program store enable output : read strobe to the external program memory via port 0 and port 2. it is activated twice each machine cycle during fetches from external program memory. when executing out of external program memory two activations of psen are skipped during each access to external data memory. psen is not activated (remains high) during no fetches from external program memory. psen can sink/source 8 lsttl inputs. it can drive cmos inputs without external pull-ups. ale 30 33 27 address latch enable output : latches the low byte of the address during access to external memory in normal operation. it is activated every six oscillator periods except during an external data memory access. ale can sink/source 8 lsttl inputs. it can drive cmos inputs without an external pull-up. ea 31 35 (34 n.c.) 29 (28 n.c.) external access input : when during reset, ea is held at a ttl high level, the cpu executes out of the internal program rom, provided the program counter is less than 32768. when ea is held at a ttl low level during reset, the cpu executes out of external program memory via port 0 and port 2. ea is not allowed to ?oat. p0.0-p0.7 32 - 39 36 - 43 30 - 37 port 0 : 8-bit open drain bidirectional i/o port. it is also the multiplexed low-order address and data bus during accesses to external memory (ad0 to ad7). during these accesses internal pull-ups are activated. port 0 can sink/source 8 lsttl inputs. v dd 40 44 38 power supply : +5 v power supply pin during normal operation, idle mode and power-down mode. symbol pin description sot 129-1 sot 187-2 sot 307-2
1997 dec 15 13 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 8 functional description 8.1 general the p83c524, p80c528 and p83c528 are stand-alone high-performance microcontrollers designed for use in real time applications such as instrumentation, industrial control, medium to high-end consumer applications and specific automotive control applications. in addition to the 80c51 standard functions, the devices provide a number of dedicated hardware functions for these applications. the p83c524 and p83c528 are control-oriented cpus with on-chip program and data memory. they can be extended with external program memory up to 64 kbytes. they can also access up to 64 kbytes of external data memory. for systems requiring extra capability, the p83c524 and p83c528 can be expanded using standard memories and peripherals. the p83c524, p80c528 and p83c528 have two software selectable modes of reduced activity for further power reduction: idle and power-down. the idle mode freezes the cpu while allowing the ram, timers, serial ports and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator causing all other chip functions to be inoperative except the wdt if it is enabled. the power-down mode can be terminated by an external reset, a wdt overflow, and in addition, by either of the two external interrupts. 8.2 instruction set execution the p83c524, p80c528 and p83c528 use the powerful instruction set of the 80c51. additional sfrs are incorporated to control the on-chip peripherals. the instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. when using a 16 mhz oscillator, 64 instructions execute in 750 ns and 45 instructions execute in 1.5 s. multiply and divide instructions execute in 3 m s (see chapter 18). 9 memory organization the central processing unit (cpu) manipulates operands in three memory spaces; these are the 64 kbyte external data memory (of which the lower 256 bytes reside in the internal aux-ram), 512 byte internal data memory (consisting of 256 bytes standard ram and 256 bytes aux-ram) and the 64 kbyte internal and external program memory. 9.1 program memory the program memory address space of the p83c528 comprises an internal and an external memory portion. the p83c528 has 32 kbyte of program memory on-chip. the program memory can be externally expanded up to 64 kbyte. if the ea pin is held high, the p83c528 executes out of the internal program memory unless the address exceeds 7fffh. locations 8000h through 0ffffh are then fetched from the external program memory. if the ea pin is held low, the p83c528 fetches all instructions from the external program memory. fig.6 illustrates the program memory address space. by setting a mask programmable security bit the rom content is protected i.e. it cannot be read out by any test mode or by any instruction in the external program memory space. the movc instructions are the only ones which have access to program code in the internal or external program memory. the ea input is latched during reset and is 'don't care' after reset. this implementation prevents reading from internal program code by switching from external program memory to internal program memory during movc instruction or an instruction that handles immediate data. table 2 lists the access to the internal and external program memory by the movc instructions when the security bit has been set to a logical one. if the security bit has been set to a logical 0 there are no restrictions for the movc instructions. fig.6 program memory address space. handbook, halfpage mbc456 - 1 external 64 k 32768 32767 00 program memory 32767 external (ea = 0) internal (ea = 1) 16383 (1) (1) only for p83c524. ( ea = 1) ( ea = 0)
1997 dec 15 14 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 table 2 internal and external program memory access with security bit set instruction access to internal program memory access to external program memory movc in internal program memory yes yes movc in external program memory no yes 9.2 internal data memory the internal data memory is divided into three physically separated parts: 256 byte of ram, 256 byte of aux-ram, and a 128 byte special function area (sfr). these parts can be addressed as follows (see table 3 and fig.11): ram 0 to 127 can be addressed directly and indirectly as in the 80c51. address pointers are r0 and r1 of the selected register bank. ram 128 to 255 can only be addressed indirectly. address pointers are r0 and r1 of the selected register bank. aux-ram 0 to 255 is indirectly addressable as the external data memory locations 0 to 255 with the movx instructions. address pointers are r0 and r1 of the selected register bank and dptr. when executing from internal program memory, an access to aux-ram 0 to 255 will not affect the ports p0, p2, p3.6 and p3.7. the sfrs can only be addressed directly in the address range from 128 to 255. an access to external data memory locations higher than 255 will be performed with the movx dptr instructions in the same way as in the 80c51 structure, i.e. with p0 and p2 as data/address bus and p3.6 and p3.7 as write and read timing signals (see figures 7, 8, 9 and 10). note that the external data memory cannot be accessed with r0 and r1 as address pointer. fig.11 shows the internal and external data memory address space. fig.12 shows the special function register (sfr) memory map. four 8-bit register banks occupy locations 0 through 31 in the lower ram area. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. the stack can be located anywhere in the internal 256 byte ram. the stack depth is only limited by the available internal ram space of 256 bytes. all registers except the program counter and the four 8-bit register banks reside in the sfr address space. table 3 internal data memory access location addressed ram 0 to 127 direct and indirect ram 128 to 255 indirect only aux-ram 0 to 255 indirect only with movx special function register (sfr) 128 to 255 direct only
1997 dec 15 15 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.7 internal program memory execution. a. without a movx. b. with a movx to the aux-ram (read and write). handbook, full pagewidth mbc458 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 cycle 1 cycle 2 ale psen rd wr p0 p0 out p2 p2 out handbook, full pagewidth mbc457 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 one machine cycle ale psen rd wr p0 p0 out p2 p2 out one machine cycle
1997 dec 15 16 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.8 internal program memory execution (continued). handbook, full pagewidth mbc460 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 cycle 1 cycle 2 ale psen rd wr p0 dpl out p0 out p2 p2 out dph out p2 out data out a. with a movx to the external data memory (read). b. with a movx to the external data memory (write). handbook, full pagewidth mbc459 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 cycle 1 cycle 2 ale psen rd wr p0 data in dpl out p0 out p2 p2 out dph out p2 out
1997 dec 15 17 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.9 external program memory execution. a. without a movx. b. with a movx to the aux-ram (read and write). handbook, full pagewidth mbc462 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale psen rd wr p0 p2 pch out cycle 1 cycle 2 pch out addrh out pch out pcl out inst in addrl out inst in pcl out p0 p2 pch out pch out addrh out pch out pcl out inst in addrl out inst in pcl out data out (read) (write) handbook, full pagewidth mbc461 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale psen rd wr p0 p2 pch out one machine cycle one machine cycle pch out pch out pch out pch out inst in pcl out inst in pcl out inst in pcl out inst in pcl out
1997 dec 15 18 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.10 external program memory execution (continued). a. with a movx to the external data memory (read). b. with a movx to the external data memory (write). handbook, full pagewidth s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale psen rd wr p0 p2 pch out cycle 1 cycle 2 pch out dph out pch out pcl out inst in dpl out inst in pcl out mbc464 data out handbook, full pagewidth s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale psen rd wr p0 p2 pch out cycle 1 cycle 2 pch out dph out pch out pcl out inst in dpl out inst in pcl out mbc463 data in
1997 dec 15 19 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.11 internal and external data memory address space. handbook, full pagewidth mbc466 - 1 ffff 0100 ff 00 00 7f 80 ff ff 80 shared address location data memory register indirect addressing direct byte addressing special function registers external data memory aux - ram 256 bytes lower 128 bytes internal ram upper 128 bytes internal ram
1997 dec 15 20 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.12 special function register (sfr) memory map. handbook, full pagewidth mbc465 - 1 f7 f6 f5 f4 f3 f2 f1 f0 f0h b e0h acc e7 e6 e5 e4 e3 e2 e1 e0 dah s1int d9h s1bit sdi/ sdo df sci/ sco de clh do bb dc rbf db wbf da str d9 ens d8 d8h s1scs ffh t3 cy d7 ac d6 fo d5 rsi d4 rso d3 ov d2 fi d1 p d0 d0h psw cdh th2 cch tl2 cbh rcap2h cah rcap2l tf2 cf exf2 ce rclk cd tclk cc exen2 cb tr2 ca c8h t2con - - - bf ps1 be pt2 bd ps bc pt1 bb px1 ba pt0 b9 px0 b8 b8h ip b0h p3 ea af es1 ae et2 ad es ac et1 ab ex1 aa et0 a9 ex0 a8 a8h ie b7 b6 b5 b4 b3 b2 b1 b0 cp/rl2 c8 c/t2 c9 a0h p2 a7 a6 a5 a4 a3 a2 a1 a0 a5h wdcon 99h sbuf sm0 9f sm1 9e sm2 9d ren 9c tb8 9b rb8 9a ti 99 ri 98 98h scon 90h p1 97 96 95 94 93 92 91 90 8dh th1 tf1 8f tr1 8e tf0 8d tr0 8c ie1 8b it1 8a ie0 89 it0 88 88h tcon 8ch th0 8bh tl1 8ah tl0 89h tmod 87h pcon 80h p0 87 86 85 84 83 82 81 80 81h 82h 83h dph dpl sp register mnemonic bit mnemonic / bit address (hex) direct byte address (hex)
1997 dec 15 21 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 9.3 addressing the p83c528 has five modes for addressing: register direct register-indirect immediate base-register plus index-register-indirect. the first three methods can be used for addressing destination operands. most instructions have a 'destination/source' field that specifies the data type, addressing methods and operands involved. for operations other than movs, the destination operand is also a source operand. access to memory addresses is as follows: register in one of the four 8-bit register banks through register, direct or register-indirect addressing. 512 bytes of internal ram through direct or register-indirect addressing. bytes 0-127 of internal ram may be addressed directly/indirectly. bytes 128-255 of internal ram share their address location with the sfrs and so may only be addressed indirectly as data ram. bytes 0-255 of aux-ram can only be addressed indirectly via movx. sfr through direct addressing at address locations 128-255. external data memory through register-indirect addressing. program memory look-up tables through base-register plus index-register-indirect addressing.
1997 dec 15 22 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 10 i/o facilities the p83c528 has four 8-bit ports. ports 0-3 are the same as in the 80c51, with the exception of the additional function of port 1. port lines p1.0 and p1.1 may be used as inputs for timer 2, p1.1 may also be used as an additional (third) external interrupt request input. port lines p1.6 and p1.7 may be selected as the scl and sda lines of serial port sio1 (i 2 c). because the i 2 c-bus may be active while the device is disconnected from v dd , these pins are provided with open drain drivers. pins p1.6 and p1.7 do not have pull-up devices when used as ports. ports 0, 1, 2, and 3 perform the following alternative functions: port 0: provides the multiplexed low-order address and data bus used for expanding the p83c528 with standard memories and peripherals. port 1: pins can be configured individually to provide: external interrupt request input (external interrupt 2); external inputs for timer/counter 2; scl and sda for the i 2 c interface. port 2: provides the high-order address bus when expanding the p83c528 with external program memory and/or external data memory. port 3: pins can be configured individually to provide: external interrupt request inputs (external interrupt 0/1); external inputs for timer/counter 0 and timer/counter 1; serial port receiver input and transmitter output control-signals to read and write external data memory. bits which are not used for the alternative functions may be used as normal bidirectional i/o pins. the generation or use of a port 1 or port 3 pin as an alternative function is carried out automatically by the p83c528 provided the associated sfr bit is high. otherwise the port pin is held at a logical low level. fig.13 i/o buffers in the p83c528 (ports 1, 2 and 3 except p1.6 and p1.7). h andbook, full pagewidth mla513 p1 p2 p3 input data read port pin 2 oscillator periods n strong pull-up i/o pin port +5 v i1 q from port latch input buffer
1997 dec 15 23 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 11 timers/counters the p83c528 contains three 16-bit timer/counters, timer 0, timer 1 and timer 2, and one 8-bit timer, the watchdog timer t3. timer 0, timer 1 and timer 2 may be programmed to carry out the following functions: measure time intervals and pulse durations count events generate interrupt requests. 11.1 timer 0 and timer 1 timers 0 and 1 each have a control bit in tmod sfr that selects the timer or counter function of the corresponding timer. in the timer function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 12 oscillator periods, the count rate is 1 12 of the oscillator frequency. in the counter function, the register is incremented in response to a high-to-low transition at the corresponding external input pin, t0 or t1. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the counter is incremented. thus, it takes two machine cycles (24 oscillator periods) to recognize a high-to-low transition. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. timer 0 and timer 1 can be programmed independently to operate in one of four modes: mode 0 8-bit timer/counter with divide-by-32 prescaler mode 1 16-bit timer/counter mode 2 8-bit timer/counter with automatic reload mode 3 timer 0: one 8-bit timer/counter and one 8-bit timer. timer 1: stopped. when timer 0 is in mode 3, timer 1 can be programmed to operate in modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. however, the overflow from timer 1 can be used to pulse the serial port transmission-rate generator. with a 16 mhz crystal, the counting frequency of these timer/counters is as follows: in the timer function, the timer is incremented at a frequency of 1.33 mhz (oscillator frequency divided by 12). in the counter function, the frequency handling range for external inputs is 0 hz to 0.66 mhz. both internal and external inputs can be gated to the timer by a second external source for directly measuring pulse duration. the timers are started and stopped under software control. each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of mode 3 as previously described.
1997 dec 15 24 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 11.1.1 t imer /c ounter m ode c ontrol register (tmod) table 4 timer/counter mode control register (address 89h) table 5 description of the tmod bits table 6 tmod m1 and m0 operating modes 76543210 timer 1 timer 0 gate c/ tm1 m0gatec/ tm1 m0 bit symbol function timer 1 7gate timer 1 gating control : when set, timer/counter '1' is enabled only while 'int1' pin is high and 'tr1' control bit is set. when cleared, timer/counter '1' is enabled whenever 'tr1' control bit is set. 6c/ t timer or counter selector : cleared for timer operation (input from internal system clock). set for counter operation (input from 't1' input pin). 5m1 operating mode : see table 6. 4m0 operating mode : see table 6. timer 0 3gate timer 0 gating control : when set, timer/counter '0' is enabled only while 'int0' pin is high and 'tr0' control bit is set. when cleared, timer/counter '0' is enabled whenever 'tr0' control bit is set. 2c/ t timer or counter selector : cleared for timer operation (input from internal system clock). set for counter operation (input from 't0' input pin). 1m1 operating mode : see table 6. 0m0 operating mode : see table 6. m1 m0 function 00 8-bit timer/counter : 'thx' with 5-bit prescaler. 01 16-bit timer/counter : 'thx' and 'tlx' are cascaded, there is no prescaler. 10 8-bit autoload timer/counter : 'thx' holds a value which is to be reloaded into 'tlx' each time it over?ows. 11 timer 0 : tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer controlled by timer 1 control bits. 11 timer 1 : timer/counter 1 stopped.
1997 dec 15 25 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 11.1.2 t imer /c ounter c ontrol r egister (tcon) table 7 timer/counter control register (address 88h) table 8 description of the tcon bits 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol function 7 tf1 timer 1 over?ow ?ag : set by hardware on timer/counter over?ow. cleared when interrupt is processed. 6 tr1 timer 1 run control bit : set/cleared by software to turn timer/counter on/off. 5 tf0 timer 0 over?ow ?ag : set by hardware on timer/counter over?ow. cleared when interrupt is processed. 4 tr0 timer 0 run control bit : set/cleared by software to turn timer/counter on/off. 3 ie1 interrupt 1 edge ?ag : set by hardware when external interrupt is detected. cleared when interrupt is processed. 2 it1 interrupt 1 type control bit : set/cleared by software to specify falling edge/low level triggered external interrupt. 1 ie0 interrupt 0 edge ?ag : set by hardware when external interrupt is detected. cleared when interrupt is processed. 0 it0 interrupt 0 type control bit : set/cleared by software to specify falling edge/low level triggered external interrupt.
1997 dec 15 26 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 11.2 timer 2 timer 2 is functionally similar to the timer 2 of the 8052ah. timer 2 is a 16-bit timer/counter which is formed by two sfrs, tl2 and th2. another pair of sfrs, rcap2l and rcap2h, form a 16-bit capture register or a 16-bit reload register. like timer 0 and 1, timer 2 can operate either as timer or as event counter. this is selected by bit c/ t2 in the t2con sfr. the timer has three operating modes: 'capture', 'autoload' and 'baud rate generator', which are selected by bits in the t2con sfr (see table 9). table 9 timer 2 operating modes 11.2.1 t imer 2c ontrol r egister (t2con) table 10 timer 2 control register (address c8h) table 11 description of the t2con bits rclk + tclk cp/ rl2 tr2 mode 0 0 1 16-bit automatic reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 off 76543210 tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 mnemonic position function tf2 t2con.7 timer 2 over?ow ?ag : set by a timer 2 over?ow and must be cleared by software. tf2 will not be set when either rclk = 1 or tclk = 1. when timer 2 interrupt is enabled, tf2 = 1 (see exf2). exf2 t2con.6 timer 2 external ?ag : set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to timer 2 interrupt routine. rclk t2con.5 receive clock ?ag : when set, causes the serial port to use timer 2 over?ow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 over?ows to be used for the receive clock. tclk t2con.4 transmit clock ?ag : when set, causes the serial port to use timer 2 over?ow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 over?ows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable ?ag : when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control : a logic 1 starts timer 2. a logic 0 stops timer 2. c/ t2 t2con.1 timer/counter select : 0 = internal timer (osc/12). 1 = external event counter (falling edge triggered). cp/ rl2 t2con.0 capture/reload ?ag : when set, capture will occur on negative transitions at t2ex if exen2 = 1. when cleared, reloads will occur upon either timer 2 over?ows or negative transitions at t2ex if exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to reload upon over?ow.
1997 dec 15 27 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 11.2.2 c apture m ode in the capture mode (see fig.14) there are two options which are selected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer/counter which on overflow sets bit tf2 (timer 2 overflow bit). tf2 can be used to generate an interrupt. if exen2 = 1, timer 2 operates as above, with the added feature that a high-to-low transition at the external input t2ex causes the current value in timer 2 registers (tl2 and th2) to be captured into registers rcap2l and rcap2h, respectively. the high-to-low transition of t2ex also causes bit exf2 in t2con to be set. exf2 can be used to generate an interrupt. 11.2.3 a utomatic r eload m ode in the automatic reload mode (see fig.15)there are two options which are selected by bit exen2 in t2con. if exen2 = 0, then a timer 2 overflow sets tf2 and causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2l and rcap2h, which are preset by software. if exen2 = 1, timer 2 operates as above, with the added feature that a high-to-low transition at the external input t2ex triggers the 16-bit reload and sets exf2. 11.2.4 b aud r ate g enerator m ode the baud rate generator mode (see fig.16) is selected by rclk = 1 and/or tclk = 1 in t2con. overflows of either timer 2 or timer 1 can be used independently for generating baud rates for transmit and receive. the baud rate generation by timer 1 and/or timer 2 is used for the serial port in mode 1 and mode 3. the baud rate generation mode is similar to the automatic reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2l and rcap2h, which are preset by software. the baud rate for the serial port in modes 1 and 3 are determined by timer 2's overflow rate as follows: timer 2 can be configured for either 'timer' or 'counter' operation. in timer operation a prescaler divides the oscillator frequency by 2 (by 12 in the previous modes) and the baud rate is given by the formula: in this mode an overflow of timer 2 does not set tf2. if exen2 = 1, a high-to-low transition at pin t2ex sets exf2 and can be used to generate an interrupt. baud rate timer 2 overflow rate 16 ------------------------------------------------------- - = baud rate oscillator frequency 32 65536 rcap2h rc ap2l (,) ] C [ ------------------------------------------------------------------------------------------------------ - = fig.14 timer 2 in capture mode. handbook, full pagewidth mbc468 - 1 tl2 (8 bits) tr2 control th2 (8 bits) rcap2l rcap2h exf2 tf2 timer 2 interrupt exen2 control c/t2 = 1 t2 pin 12 osc transition detector t2ex pin c/t2 = 0
1997 dec 15 28 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.15 timer 2 in automatic reload mode. handbook, full pagewidth mbc469 - 1 tl2 (8 bits) tr2 control th2 (8 bits) rcap2l rcap2h exf2 tf2 timer 2 interrupt exen2 control c/t2 = 0 c/t2 = 1 t2 pin 12 osc transition detector t2ex pin reload fig.16 timer 2 in baud rate generator mode. handbook, full pagewidth mbc470 - 1 tl2 (8 bits) tr2 control th2 (8 bits) rcap2l rcap2h exf2 exen2 control c/t2 = 0 c/t2 = 1 t2 pin 2 osc transition detector t2ex pin "timer 2" interrupt (additional external interrupt) (note: divided by 2 not by 12) 16 rclk 16 tclk rx clock tx clock smod 10 10 1 0 2 timer 1 overflow
1997 dec 15 29 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 11.3 watchdog timer t3 the watchdog timer (wdt) see fig.17, consists of an 11-bit prescaler and an 8-bit timer formed by sfr t3. the prescaler is incremented by an on-chip oscillator with a fixed frequency of 1 mhz. the maximum tolerance on this frequency is - 50% and +100%. the 8-bit timer increments every 2048 cycles of the on-chip oscillator. when a timer overflow occurs, the microcontroller is reset and a reset-output-pulse of 16 x 2048 cycles of the on-chip oscillator is generated at pin rst. the internal reset signal is not inhibited when the external rst pin is kept low by e.g. an external reset circuit. the reset signal drives ports 1, 2 and 3 outputs into the high state and port 0 into high impedance, no matter if the xtal-clock is running or not. the wdt is controlled by wdcon sfr with the direct address location a5h. wdcon can be read and written by software. a value of a5h in wdcon halts the on-chip oscillator and clears both the prescaler and timer t3. after reset, wdcon contains a5h. every value other than a5h in wdcon enables the wdt. when the wdt is enabled it runs independent of the xtal-clock. timer t3 can be read on the fly. timer t3 can be written only if wdcon has previously been loaded with 5ah, otherwise t3 and the prescaler are not affected. a successful write operation to t3 also clears the prescaler and clears wdcon. during a read or write operation addressing t3, the output of the on-chip oscillator is inhibited to prevent timing problems due to asynchronous increments of t3. to prevent an overflow of the wdt, the user program has to reload t3 within periods that are shorter than the programmed watchdog time interval. this time interval is determined by the 8-bit reload value that is written into register t3. the advantages of this implementation are: only an internal reset connection to the microcontroller core the power-down mode and the watchdog (wdt) function can be used concurrently the wdt also monitors the xtal oscillator. in case of a failure the port outputs are forced to a defined high state interference will not disable the wdt because it is unlikely that it will force wdcon to a5h tolerances of the on-chip oscillator can be adjusted by testing the t3 value and adapting the reload value the wdt can be enabled and disabled under control of the user software. this gives the possibility to use both the watchdog function and the power-down function the direct address a5h of wdcon and its disable value a5h will not unintentionally be present at a random location in the field of program code, except for immediate data, because the opcode a5h is not used in the instruction set. watchdog time interval 256 t3 ) ( C [] 2048 on-chip oscillator frequency ------------------------------------------------------------------------ - = fig.17 watchdog timer t3. handbook, full pagewidth mbc471 - 1 8 - bit timer t3 11 - bit prescaler wdcon clear input a5h 5ah clear on - chip - oscillator halt write read clear wr - t3 rd - t3 over-flow v dd v ss internal reset rst this signal is active if wdcon contains this hex value ibs r rst (1) (1) (1)
1997 dec 15 30 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 12 serial port (uart) the serial port is functionally similar to the implementation in the 8052ah, with the possibility of two different baud rates for receive and transmit with timer 1 and timer 2 as baud rate generators. it is full duplex, meaning it can receive and transmit simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. however, if the first byte still has not been read by the time the reception of the second byte is complete, one of the bytes will be lost. the serial port receive and transmit registers are both accessed as sbuf sfr. writing to sbuf loads the transmit register, and reading sbuf accesses the physically separate receive register. the serial port can operate in one of four modes: mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb ?rst). the baud rate is ?xed at 1/12 the oscillator frequency. mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb ?rst), and a stop bit (1). on receive, the stop bit goes into rb8 in scon sfr. the baud rate is variable. mode 2 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except the baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. in mode 0, reception is initiated by the condition ri = 0 and ren = 1. reception is initiated by incoming start bit if ren = 1 in the other modes.
1997 dec 15 31 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 12.1 serial port control register (scon) table 12 serial port control register (address 98h) table 13 description of the scon bits 12.2 sm0 and sm1 operating modes (scon) scon bits sm0 and sm1 can operate in the following modes (see table 14): table 14 sm0 and sm1 operating modes 76543210 sm0 sm1 sm2 ren tb8 rb8 ti ri bit symbol function 7 sm0 see table 14. 6 sm1 see table 14. 5 sm2 enables the multiprocessor communication feature in modes 2 and 3 . in these modes, if sm2 is set to 1 then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1, then ri will not be activated if a valid stop bit is not received. in mode 0, sm2 should be 0. 4 ren enables serial reception . set and cleared by software as required. 3 tb8 9th data bit that will be transmitted in modes 2 and 3 . set and cleared by software as required. 2 rb8 in modes 2 and 3, rb8 is the 9th data bit that is received . in mode 1, if sm2 = 0, rb8 is the stop bit that is received. in mode 0, rb8 is not used. 1ti transmit interrupt ?ag . it is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. ti must be cleared by software. 0ri receive interrupt ?ag . it is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes (except: see sm2). ri must be cleared by software. mode sm0 sm1 description baud rate 0 0 0 shift register 1 12 f osc 1 0 1 8-bit uart variable 2 1 0 9-bit uart 1 32 f osc , 1 64 f osc 3 1 1 9-bit uart variable
1997 dec 15 32 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 13 bit-level i 2 c interface this bit-level serial i/o interface supports the i 2 c-bus (see fig.18). p1.6/scl and p1.7/sda are the serial i/o pins. these two pins meet the i 2 c specification concerning the input levels and output drive capability. consequently, these pins have an open drain output configuration. all four modes of the i 2 c-bus are supported: master transmitter master receiver slave transmitter slave receiver. the advantages of the bit-level i 2 c hardware compared with a full software i 2 c implementation are: the hardware can generate the scl pulse testing a single bit (rbf respectively, wbf) is sufficient as a check for error free transmission. the bit-level i 2 c hardware operates on serial bit level and performs the following functions: filtering the incoming serial data and clock signals recognizing the start condition generating a serial interrupt request si after reception of a start condition and the first falling edge of the serial clock recognizing the stop condition recognizing a serial clock pulse on the scl line latching a serial bit on the sda line (sdi) stretching the scl low period of the serial clock to suspend the transfer of the next serial data bit setting read bit finished (rbf) when the scl clock pulse has finished and write bit finished (wbf) if there is no arbitration loss detected (i.e. sda = 0 while sdo = 1) setting a serial clock low-to-high detected (clh) flag setting a bus busy (bb) flag on a start condition and clearing this flag on a stop condition releasing the scl line and clearing the clh, rbf and wbf flags to resume transfer of the next serial data bit generating an automatic clock if the single bit data register s1bit is used in master mode. the following functions must be done in software: handling the i 2 c start interrupts converting serial to parallel data when receiving converting parallel to serial data when transmitting comparing the received slave address with its own interpreting the acknowledge information guarding the i 2 c status if rbf or wbf = 0. additionally, if acting as master: generating start and stop conditions handling bus arbitration generating serial clock pulses if s1bit is not used. three sfrs control the bit-level i 2 c interface: s1int, s1bit and s1scs.
1997 dec 15 33 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.18 bit level i 2 c interface block diagram. handbook, full pagewidth mbc484 rscs dq ens c wscs ib0 pd dis en rscs dq str c wscs ib1 rscs ib2 rscs ib3 wbf rbf rscs sq bb r ib4 sdiqn sdoq clhq staqn bbq fscln start stop rscs sq clh r ib5 fscl wscs ib5 rsbit wsbit rscs qd sco c ib6 auto - clock generator rsbit wsbit wscs fscl sq st r staq fscl strq qn en sq sta r si to interrupt logic scl filter dis fscl sda filter fsda qd sdo c ib7 wsbit wscs rsbit rscs q d sdi c dis qn fscl en start stop wsbit rsbit fsda fscl wsint fsda fscl ib7 wsbit rsbit p1.7 / sda p1.7 / scl ibx : internal data bus rscs : read wscs : write rsbit : read wsbit : write wsint : write s1int s1scs s1bit (with auto-clock)
1997 dec 15 34 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 13.1 i 2 c interrupt register (s1int) table 15 i 2 c interrupt register (address dah) (1) note 1. si bit : writing a logic 0 clears this bit, writing a logic 1 has no effect. table 16 description of the s1int bits 13.2 single-bit data register with i 2 c auto-clock (s1bit) table 17 single-bit data register with i 2 c auto-clock (address d9h) (1) note 1. access of the s1bit sfr clears si, clh, rbf and wbf. it starts the auto-clock if sco = 0. table 18 description of the s1bit bits 76543210 sixxxxxxx bit symbol function 7si serial interrupt request (si) ?ag : if a start condition occurs the si ?ag in the s1int sfr is set on the falling edge of the ?ltered serial clock. if si = 1 is detected during a transfer this can be a 'spurious start' error condition. if no transfer is taking place the si = 1 is a start from an external master. provided the bits ea and es1 in ie sfr are set, si then generates an interrupt so that a slave address receive routine can be started. si can be cleared by accessing the s1bit register or by writing '00' to s1int. also after reception of a start condition, the low period of the clock pulse is stretched, suspending the serial transfer to allow the software to take action. this clock stretching is ended by a read or write access to s1bit. 6 to 0 - x = unde?ned during read, don't care during write. 76543210 read sdi0000000 write sdoxxxxxxx bit symbol function 7 sdo/sdi serial data output (sdo) and the ?ltered serial data input (sdi) . sdi data is latched on the rising edge of the ?ltered serial clock. s1bit.7 accesses the same memory locations as s1scs.7. s1bit sfr is not bit-addressable. 6 to 0 - x = don't care.
1997 dec 15 35 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 13.2.1 r eading or w riting the s1bit sfr reading or writing the s1bit sfr starts an i 2 c bit i/o sequence: some flags are cleared (si, clh, rbf, wbf), clock stretching is finished and the auto-clock is started. an auto-clock pulse is 'or-ed' with sco and thus will be output only if the sco flag has been set to 0. sco = 1 inhibits the auto-clock start, so a dummy read or write of s1bit sfr can be used to finish clock stretching and clear si, clh, rbf and wbf if the auto-clock is not used. the auto-clock is an active high scl pulse that starts 28 xtal clock periods after the sdi read or sdo write via s1bit. the duration of the auto-clock pulse is 100 xtal clock periods. if the scl line is kept low by any device that wants to hold up the bus transfer, the auto-clock counter waits after 20 xtal clock periods so that the auto-clock pulse length will be at least 80 xtal clock periods (5 m s at f osc = 16 mhz). every bit i/o should be followed by a rbf or wbf bit test. a bit transfer has been finished successfully if after reading a bit the rbf flag is 1 or after writing a bit the wbf flag is 1. when after reading a bit the rbf flag is still 0, the bus status just before the s1scs status read can be determined as follows: if clh = 0 then a bus device is still stretching the clock if sci = 1 while clh = 1 then the scl pulse is not finished if bb = 0 there has been a stop condition. when after writing a bit the wbf flag is still 0 and none of the 3 status conditions mentioned for rbf are found then a 'bus arbitration lost' condition will be the cause. this can be determined also from the states of the received bit and the last transmitted bit: 'arbitration loss' if sdo = 1 and sdi = 0. 13.3 control and status register for the i 2 c-bus (s1scs) table 19 control and status register for the i 2 c-bus (address d8h) notes 1. sdi and sci bits : read-modify-write operations like 'setb bit' or 'clr bit' access sdo and sco for reading and writing. 2. clh bit : writing a logic 0 clears this bit, writing a 1 has no effect. 3. rbf and wbf bits : writing a logic 0 to clh also clears these bits. 4. x = don't care. 76543210 read sdi (1) sci (1) clh (2) bb rbf (3) wbf (4) str ens write sdo sco clh (2) x x x str ens
1997 dec 15 36 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 table 20 description of the s1scs bits bit symbol function 7 sdo/sdi serial data output and the ?ltered serial data input . sdi data is latched on the rising edge of the ?ltered serial clock. s1scs.7 accesses the same memory locations as s1bit.7. access of the data bit via s1scs will not start an auto-clock pulse. 6 sco/sci serial clock output and the ?ltered serial clock input . serial clock output sco is 'or-ed' with the auto-clock. if sco = 1 the auto-clock output is inhibited. the internal clock stretching logic and external devices can pull the scl line low. if the auto-clock is not used, the scl line has to be controlled by setting sco = 1, waiting for clh = 1 and setting sco = 0 after the speci?ed scl high time. (because of the input ?lter, clh will be set at least 8 xtal clock periods after the scl low-to-high transition.) 5 clh serial clock low-to-high transition ?ag : set with a rising edge of the ?ltered serial clock. clh = 1 indicates that, since the last clh reset, a new valid data bit has been latched in sdi. clh can be reset by writing a 0 to s1scs.5 or by a read/write of s1bit. clearing clh also clears rbf and wbf. 4bb bus busy ?ag : indicating that there has been a start condition that was not yet followed by a stop condition. 3 rbf read bit finished ?ag : indicating a successful bit read. rbf = 1 implies the following conditions: clh = 1: scl had a rising edge sci = 0: the scl pulse has finished si = 0: no start condition occurred bb = 1: no stop condition occurred the rbf ?ag can be cleared by clearing the clh ?ag. 2 wbf write bit finished ?ag : indicating a successful bit write. the same conditions as for rbf are true and also no 'arbitration loss' condition occurred. arbitration is lost if a 1 data bit in sdo was over-ruled on sda by an external device. the wbf ?ag can be cleared by clearing the clh ?ag. 1 str stretch control ?ag . str = 1 enables stretching of all scl low periods. this allows the processor in i 2 c slave mode to react on a fast master. the str ?ag remains set until cleared by writing a 0 to s1scs.1. the stretch (st) ?ag (not readable) pulls the serial clock low while st = 1. the st ?ag is set on the falling edge of the ?ltered serial clock if str = 1. it is also set after reception of a start condition, regardless of the str contents. st is cleared with a read or write of s1bit. 0 ens enable serial i/o ?ag . ens = 1 enables the start detection and clock stretching logic. ens = 0 can be used to switch off the i 2 c-bus hardware. note that the sdo and sco control ?ags must be set to 1 before ens is set to avoid pulling scl or sda lines to 0.
1997 dec 15 37 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 14 interrupt system the p83c528 contains the same interrupt structure as the pcb80c51bh, but with a seven-source interrupt structure with two priority levels (see fig.19). the external interrupts int0 and int1 can each be either level-activated or transition-activated, depending on bits it0 and it1 in tcon sfr. the flags that actually generate these interrupts are bits ie0 and ie1 in tcon. when an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to, only if the interrupt was transition-activated. if the interrupt was level-activated then the interrupt request flag remains set until the external interrupt pin intx goes high. the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter register (except for timer 0 in mode 3 of the serial interface). when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. the serial port interrupt is generated by the logical 'or' of ri and ti. neither of these flags is cleared by hardware. the service routine will normally have to determine whether it was ri or ti that generated the interrupt, and the bit will have to be cleared by software. the timer 2 interrupt is generated by the logical or of tf2 and exf2. neither of these flags is cleared by hardware. in fact the service routine may have to determine whether it was tf2 or exf2 that generated the interrupt, and the bit will have to be cleared by software. an additional (third) external interrupt is available, if timer 2 is not used as timer/counter or if timer 2 is used in baud rate generator mode. that external interrupt 2 is falling edge triggered. it shares the timer 2 interrupt vector, interrupt enable and interrupt priority bits. if bit t2con.3/exen2 = 1, a high-to-low transition at pin p1.1/t2ex sets the interrupt request flag t2con.6/exf2 and can be used to generate an external interrupt. the i 2 c interrupt is generated by si in s1int. this flag has to be cleared by software. all of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware, with the exception of the i 2 c interrupt request flag si, which cannot be set by software. that is, interrupts can be generated or pending interrupts can be cancelled in software. fig.19 p83c528 interrupt sources. handbook, halfpage mbc481 - 1 ie1 0 1 ie0 0 1 interrupt sources int0 tf2 exf2 si tf0 int1 tf1 ti ri
1997 dec 15 38 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 14.1 interrupt enable register (ie) table 21 interrupt enable register (address a8h) table 22 description of the ie bits 14.2 interrupt priority register (ip) table 23 interrupt priority register (address b8h) 76543210 ea es1 et2 es et1 ex1 et0 ex0 bit symbol function 7 ea general enable/disable control: 0= no interrupt is enabled 1= any individually enabled interrupt will be accepted 6 es1 enable bit-level i 2 c i/o interrupt 5 et2 enable timer 2 interrupt 4 es enable serial port interrupt 3 et1 enable timer 1 interrupt 2 ex1 enable external interrupt 1 1 et0 enable timer 0 interrupt 0 ex0 enable external interrupt 0 76543210 - ps1 pt2 ps pt1 px1 pt0 px0
1997 dec 15 39 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 14.3 interrupt vectors the interrupt vectors are listed in table 25. table 24 description of the ip bits table 25 interrupt vectors bit symbol function 7 - reserved 6 ps1 bit-level i 2 c interrupt priority level 5 pt2 timer 2 interrupt priority level 4ps serial port interrupt priority level 3 pt1 timer 1 interrupt priority level 2 px1 external interrupt 1 priority level 1 pt0 timer 0 interrupt priority level 0 px0 external interrupt 0 priority level number source priority within level vector address 1 ie0 (highest) 0003h 2 tf2+exf2 - 002bh 3 si (i 2 c) - 0053h 4 tf0 - 000bh 5 ie1 - 0013h 6 tf1 - 001bh 7 ri + ti (lowest) 0023h
1997 dec 15 40 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 15 idle and power-down operation idle mode operation permits the interrupt, serial ports and timer blocks to function while the cpu is halted. the following functions remain active during idle mode. these functions may generate an interrupt or reset and thus end the idle mode: timer 0, timer 1, timer 2, watchdog timer uart, i 2 c-interface external interrupt the power-down operation freezes the oscillator. the power-down mode can only be activated by setting the pd bit in the pcon register (see fig.20). fig.20 internal idle and power-down clock configuration. handbook, full pagewidth mbc477 - 1 oscillator clock generator interrupts serial ports timer blocks cpu idl pd xtal1 xtal2
1997 dec 15 41 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 15.1 power control register (pcon) special modes are activated by software via the pcon sfr. pcon is not bit addressable. the reset value of pcon is 0xxx0000. table 26 power control register (address 87h) table 27 description of the pcon bits notes 1. if logic 1s are written to pd and idl at the same time, pd takes precedence. 2. user software should not write 1s to reserved bits. these bits may be used in future 80c51 family products to invoke new features. 76543210 smod --- gf1 gf0 pd idl bit symbol function 7 smod double baud rate bit : when set to logic 1 the baud rate is doubled when timer 1 is used to generate baud rate, and the serial port is used in modes 1, 2 or 3. 6 - reserved for future use 5 - reserved for future use 4 - reserved for future use 3 gf1 general-purpose ?ag bit 2 gf0 general-purpose ?ag bit 1pd power-down bit : setting this bit activates power-down mode 0 idl idle mode bit : setting this bit activates the idle mode.
1997 dec 15 42 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 15.2 idle mode the instruction that sets pcon.0 is the last instruction executed in the normal operating mode before idle mode is activated. once in the idle mode, the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle mode. the status of external pins during idle mode is shown in table 28. there are three ways to terminate the idle mode: activation of any enabled interrupt will cause pcon.0 to be cleared by hardware terminating idle mode. the interrupt is serviced, and following return from interrupt instruction reti, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to pcon.0. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during the idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. the second way of terminating the idle mode is with an external hardware reset. since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. the third way of terminating the idle mode is by internal watchdog reset. 15.3 power-down mode the instruction that sets pcon.1 is the last executed prior to going into the power-down mode. the oscillator is stopped. note that the power-down mode also can be entered when the watchdog has been enabled. the power-down mode can be terminated by an external reset in the same way as in the 80c51 or in addition by any one of the two external interrupts, ie0 or ie1 (see section 15.4). a reset generated by the wdt terminates the power-down mode in the same way as an external reset. the status of the external pins during power-down mode is shown in table 28. if the power-down mode is activated while in external program memory, the port data that is held in the p2 sfr is restored to port 2. if the data is a logic 1, the port pin is held high during the power-down mode by the strong pull-up transistor p1 (see fig.13). table 28 status of the external pins during idle and power-down modes mode memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 port data port data port data port data idle external 1 1 ?oating port data address port data power-down internal 0 0 port data port data port data port data power-down external 0 0 ?oating port data port data port data
1997 dec 15 43 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 15.4 wake-up from power-down mode the power-down mode of the p83c528 can also be terminated by any one of the two external interrupts, ie0 or ie1. a termination with an external interrupt does not affect the internal data memory and does not affect the special function registers (sfrs). this gives the possibility to exit power-down without changing the port output levels. to terminate the power-down mode with an external interrupt, ie0 or ie1 must be switched to be level-sensitive and must be enabled. the external interrupt input signal int0 and int1 must be kept low till the oscillator has restarted and stabilized (see fig.21). in order to prevent any interrupt priority problems during wake-up, the priority of the desired wake-up interrupt should be higher than the priorities of all other enabled interrupt sources. the instruction following the one that put the device into the power-down mode will be the first one which will be executed after an interrupt has been serviced. table 29 internal registers status after a reset register contents acc 00h b 00h dph, dpl 00h ie 0000 0000b ip x000 0000b pch, pcl 00h pcon 0xxx 0000b psw 00h p0 to p3 ffh sbuf indeterminate scon 00h sp 07h tcon 00h tmod 00h th0, tl0 00h th1, tl1 00h t2con 00h th2, tl2 00h rcap2h, rcap2l 00h s1bit x000 0000b s1int 0xxx xxxxb s1scs xxx0 0000b t3 00h wdcon a5h fig.21 wake up by external interrupt input. mbc508 - 1 oscillator stopped oscillator start up min. 20 ms power down internal timing stopped c1 c1 c1 c2 idle mode lcall interrupt routine set external interrupt latch int0 / int1 int1 1 cycle int0 2 cycles interrupts are polled
1997 dec 15 44 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 16 oscillator circuit the oscillator circuit of the p83c528 is a single-stage inverting amplifier in a pierce oscillator configuration. the circuitry between the xtal1 and xtal2 is basically an inverter biased to the transfer point. either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuitry. both are operated in parallel resonance. xtal1 is the high gain amplifier input, and xtal2 is the output (see fig.22). to drive the p83c528 externally, xtal1 is driven from an external source and xtal2 left open-circuit (see fig.23). fig.22 p83c528 oscillator circuit. handbook, halfpage c1 xtal1 xtal2 20 pf c2 mbc473 20 pf fig.23 driving the p83c528 from an external source. h andbook, halfpage xtal1 xtal2 mbc472 external clock (not ttl compatible) not connected 17 reset circuit the reset circuitry for the p83c528 is connected to the reset pin rst. a schmitt trigger is used at the input for noise rejection. the output of the schmitt trigger is sampled by the reset circuitry every machine cycle. a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods). the cpu responds by executing an internal reset. during reset ale and psen output a high level. in order to perform a correct reset, this level must not be affected by external elements. with the p83c528, the rst line can also be pulled high internally by a pull-up transistor activated by the wdt t3. the length of the reset pulse from t3 is 16 x 2048 cycles of the on-chip watchdog oscillator. if the wdt is also used to reset external devices, the usual capacitor arrangement should not be connected to rst pin. instead, an extra circuit should be used to perform the power-on reset operation. it should be remembered that a timer t3 overflow, if enabled, will force a reset condition to the p83c528 by an internal connection, whether the output rst is tied low or not (see fig.24). the internal reset is executed during the second cycle in which rst is pulled high and is repeated every cycle until rst goes low. it leaves the internal registers as shown by table 29. fig.24 on-chip reset configuration. handbook, halfpage mbc476 - 1 schmitt trigger reset circuitry overflow timer t3 v dd rst on-chip resistor rst r
1997 dec 15 45 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 17.1 power-on reset when v dd is turned on, and provided its rise-time does not exceed 10 ms, an automatic reset can be obtained by connecting the rst pin to v dd via a 2.2 m f capacitor. when the power is switched on, the voltage on the rst pin is equal to v dd minus the capacitor voltage, and decreases from v dd as the capacitor charges through the internal resistor (r rst ) to ground. the larger the capacitor, the more slowly v rst decreases. v rst must remain above the lower threshold of the schmitt trigger long enough to effect a complete reset. the time required is the oscillator start-up time, plus 2 machine cycles, or 16 x 2048 cycles of the on-chip watchdog oscillator if it is running, whichever is longer (see fig.25). fig.25 power-on reset. handbook, halfpage v dd v dd rst 2.2 m f r rst mbc474 p83c528
1997 dec 15 46 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 18 instruction set the instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. when using a 12 mhz oscillator, 64 instructions execute in 1 cycle (1 m s) and 45 instructions execute in 2 cycles (2 m s). multiply and divide instructions execute in 4 cycles (4 m s). table 30 instruction set description: arithmetic operations mnemonic description bytes cycles opcode (hex) arithmetic operations add a,rr add register to a 1 1 2* add a,direct add direct byte to a 2 1 25 add a,@ri add indirect ram to a 1 1 26, 27 add a,#data add immediate data to a 2 1 24 addc a,rr add register to a with carry ?ag 1 1 3* addc a,direct add direct byte to a with carry ?ag 2 1 35 addc a,@ri add indirect ram to a with carry ?ag 1 1 36, 37 addc a,#data add immediate data to a with carry ?ag 2 1 34 subb a,rr subtract register from a with borrow 1 1 9* subb a,direct subtract direct byte from a with borrow 2 1 95 subb a,@ri subtract indirect ram from a with borrow 1 1 96, 97 subb a,#data subtract immediate data from a with borrow 2 1 94 inc a increment a 1 1 04 inc rr increment register 1 1 0* inc direct increment direct byte 2 1 05 inc @ri increment indirect ram 1 1 06, 07 dec a decrement a 1 1 14 dec rr decrement register 1 1 1* dec direct decrement direct byte 2 1 15 dec @ri decrement indirect ram 1 1 16, 17 inc dptr increment data pointer 1 2 a3 mul ab multiply a and b 1 4 a4 div ab divide a by b 1 4 84 da a decimal adjust a 1 1 d4
1997 dec 15 47 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 table 31 instruction set description: logic operations mnemonic description bytes cycles opcode (hex) logic operations anl a,rr and register to a 1 1 5* anl a,direct and direct byte to a 2 1 55 anl a,@ri and indirect ram to a 1 1 56, 57 anl a,#data and immediate data to a 2 1 54 anl direct,a and a to direct byte 2 1 52 anl direct,#data and immediate data to direct byte 3 2 53 orl a,rr or register to a 1 1 4* orl a,direct or direct byte to a 2 1 45 orl a,@ri or indirect ram to a 1 1 46, 47 orl a,#data or immediate data to a 2 1 44 orl direct,a or a to direct byte 2 1 42 orl direct,#data or immediate data to direct byte 3 2 43 xrl a,rr exclusive-or register to a 1 1 6* xrl a,direct exclusive-or direct byte to a 2 1 65 xrl a,@ri exclusive-or indirect ram to a 1 1 66, 67 xrl a,#data exclusive-or immediate data to a 2 1 64 xrl direct,a exclusive-or a to direct byte 2 1 62 xrl direct,#data exclusive-or immediate data to direct byte 3 2 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 rl a rotate a left 1 1 23 rlc a rotate a left through the carry ?ag 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through the carry ?ag 1 1 13 swap a swap nibbles within a 1 1 c4
1997 dec 15 48 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 table 32 instruction set description: data transfer note 1. mov a,acc is not permitted. mnemonic description bytes cycles opcode (hex) data transfer mov a,rr move register to a 1 1 e* mov a,direct (note 1) move direct byte to a 2 1 e5 mov a,@ri move indirect ram to a 1 1 e6, e7 mov a,#data move immediate data to a 2 1 74 mov rr,a move a to register 1 1 f* mov rr,direct move direct byte to register 2 2 a* mov rr,#data move immediate data to register 2 1 7* mov direct,a move a to direct byte 2 1 f5 mov direct,rr move register to direct byte 2 2 8* mov direct,direct move direct byte to direct 3 2 85 mov direct,@ri move indirect ram to direct byte 2 2 86, 87 mov direct,#data move immediate data to direct byte 3 2 75 mov @ri,a move a to indirect ram 1 1 f6, f7 mov @ri,direct move direct byte to indirect ram 2 2 a6, a7 mov @ri,#data move immediate data to indirect ram 2 1 76, 77 mov dptr,#data 16 load data pointer with a 16-bit constant 3 2 90 movc a,@a+dptr move code byte relative to dptr to a 1 2 93 movc a,@a+pc move code byte relative to pc to a 1 2 83 movx a,@ri move external ram (8-bit address) to a 1 2 e2, e3 movx a,@dptr move external ram (16-bit address) to a 1 2 e0 movx @ri,a move a to external ram (8-bit address) 1 2 f2, f3 movx @dptr,a move a to external ram (16-bit address) 1 2 f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a,rr exchange register with a 1 1 c* xch a,direct exchange direct byte with a 2 1 c5 xch a,@ri exchange indirect ram with a 1 1 c6, c7 xchd a,@ri exchange low-order digit indirect ram with a 1 1 d6, d7
1997 dec 15 49 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 table 33 instruction set description: boolean variable manipulation, program and machine control mnemonic description bytes cycles opcode (hex) boolean variable manipulation clr c clear carry ?ag 1 1 c3 clr bit clear direct bit 2 1 c2 setb c set carry ?ag 1 1 d3 setb bit set direct bit 2 1 d2 cpl c complement carry ?ag 1 1 b3 cpl bit complement direct bit 2 1 b2 anl c,bit and direct bit to carry ?ag 2 2 82 anl c,/bit and complement of direct bit to carry ?ag 2 2 b0 orl c,bit or direct bit to carry ?ag 2 2 72 orl c,/bit or complement of direct bit to carry ?ag 2 2 a0 mov c,bit move direct bit to carry ?ag 2 1 a2 mov bit,c move carry ?ag to direct bit 2 2 92 program and machine control acall addr11 absolute subroutine call 2 2 1addr lcall addr16 long subroutine call 3 2 12 ret return from subroutine 1 2 22 reti return from interrupt 1 2 32 ajmp addr11 absolute jump 2 2 1addr ljmp addr16 long jump 3 2 02 sjmp rel short jump (relative address) 2 2 80 jmp @a+dptr jump indirect relative to the dptr 1 2 73 jz rel jump if a is zero 2 2 60 jnz rel jump if a is not zero 2 2 70 jc rel jump if carry ?ag is set 2 2 40 jnc rel jump if carry ?ag is not set 2 2 50 jb bit,rel jump if direct bit is set 3 2 20 jnb bit,rel jump if direct bit is not set 3 2 30 jbc bit,rel jump if direct bit is set and clear bit 3 2 10 cjne a,direct,rel compare direct to a and jump if not equal 3 2 b5 cjne a,#data,rel compare immediate to a and jump if not equal 3 2 b4 cjne rr,#data,rel compare immediate to register and jump if not equal 32b* cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 2 b6, b7 djnz rr,rel decrement register and jump if not zero 2 2 d* djnz direct,rel decrement direct and jump if not zero 3 2 d5 nop no operation 1 1 00
1997 dec 15 50 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 table 34 description of the mnemonics in the instruction set mnemonic description data addressing modes rr working register r0-r7. direct 128 internal ram locations and any special function register (sfr). @ri indirect internal ram location addressed by register r0 or r1 of the actual register bank. #data 8-bit constant included in instruction. #data 16 16-bit constant included as bytes 2 and 3 of instruction. bit direct addressed bit in internal ram or sfr. addr16 16-bit destination address. used by lcall and ljmp. the branch will be anywhere within the 64 kbytes program memory address space. addr11 11-bit destination address. used by acall and ajmp. the branch will be within the same 2 kbytes page of program memory as the ?rst byte of the following instruction. rel signed (two's complement) 8-bit offset byte. used by sjmp and all conditional jumps. range is - 128 to +127 bytes relative to ?rst byte of the following instruction. hexadecimal opcode cross-reference * 8, 9, a, b, c, d, e, f. 11, 31, 51, 71, 91, b1, d1, f1. 01, 21, 41, 61, 81, a1, c1, e1.
1997 dec 15 51 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 35 instruction map note 1. mov a, acc is not a valid instruction. first hexadecimal character of opcode ? second hexadecimal character of opcode ? 0123 456789abcdef 0 nop ajmp addr11 ljmp addr16 rr a inc a inc direct inc @ri inc rr 0 1 01234567 1 jbc bit,rel acall addr11 lcall addr16 rrc a dec a dec direct dec @ri dec rr 0 1 01234567 2 jb bit,rel ajmp addr11 ret rl a add a,#data add a,direct add a,@ri add a,rr 0 1 01234567 3 jnb bit,rel acall addr11 reti rlc a addc a,#data addc a,direct addc a,@ri addc a,rr 0 1 01234567 4 jc rel ajmp addr11 orl direct,a orl direct,#data orl a,#data orl a,direct orl a,@ri orl a,rr 0 1 01234567 5 jnc rel acall addr11 anl direct,a anl direct,#data anl a,#data anl a,direct anl a,@ri anl a,rr 0 1 01234567 6 jz rel ajmp addr11 xrl direct,a xrl direct,#data xrl a,#data xrl a,direct xrl a,@ri xrl a,rr 0 1 01234567 7 jnz rel acall addr11 orl c,bit jmp @a+dptr mov a,#data mov direct,#data mov @ri,#data mov rr,#data 0 1 01234567 8 sjmp rel ajmp addr11 anl c,bit movc a,@a+pc div ab mov direct,direct mov direct,@ri mov direct,rr 0 1 01234567 9 mov dtpr,#data16 acall addr11 mov bit,c movc a,@a+dptr subb a,#data subb a,direct subb a,@ri sub a,rr 0 1 01234567 a orl c,/bit ajmp addr11 mov bit,c inc dptr mul ab mov @ri,direct mov rr,direct 0 1 01234567 b anl c,/bit acall addr11 cpl bit cpl c cjne a,#data,rel cjne a,direct,rel cjne @ri,#data,rel cjne rr,#data,rel 0 1 01234567 c push direct ajmp addr11 clr bit clr c swap a xch a,direct xch a,@ri xch a,rr 0 1 01234567 d pop direct acall addr11 setb bit setb c da a djnz direct,rel xchd a,@ri djnz rr,rel 0 1 01234567 e movx a,@dtpr ajmp addr11 movx a,@ri clr a mov a,direct (1) mov a,@ri mov a,rr 0 1 0 1 01234567 f movx @dtpr,a acall addr11 movx @ri,a cpl a mov direct,a mov @ri,a mov rr,a 0 1 0 1 01234567
1997 dec 15 52 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 19 limiting values in accordance with the absolute maximum system (iec 134) symbol parameter min. max. unit v dd supply voltage range - 0.5 +6.0 v v i all input voltages - 0.5 v dd +0.5 v p tot total power dissipation - 1w t stg storage temperature range - 65 +150 c t amb operating ambient temperature range: version xbx 0 +70 c version xfx - 40 +85 c
1997 dec 15 53 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 20 dc characteristics v dd =5v 10%; v ss =0v;t amb = 0 to +70 c; - 40 to +85 c. all voltages with respect to v ss unless otherwise speci?ed. symbol parameter conditions min. max. unit supply v dd supply voltage range 4.5 5.5 v i dd supply current operating modes, note 1 v ddmax , 16 mhz v ddmax , 24 mhz - 33 43 ma ma i id supply current idle mode, note 2 v ddmax , 16 mhz v ddmax , 24mhz - 6 7.5 ma ma i pd supply current power - down mode 2 v v dd v ddmax ; note 3 - 100 m a inputs v il low level input voltage (except ea, p1.6, p1.7) - 0.5 0.2 v dd - 0.1 v v il1 low level input voltage ea - 0.5 0.2 v dd - 0.3 v v il2 low level input voltage p1.6, p1.7 note 6 - 0.5 0.3 v dd v v ih high level input voltage (except rst, xtal1, p1.6, p1.7) 0.2 v dd +0.9 v dd +0.5 v v ih1 high level input voltage rst, xtal1 0.7 v dd v dd +0.5 v v ih2 high level input voltage p1.6, p1.7 note 6 0.7 v dd 5.5 v i il low level input current ports 1, 2 and 3 (except p1.6 and p1.7) v i = 0.45 v -- 50 m a i tl input current high-to-low transition ports 1, 2 and 3 (except p1.6 and p1.7) v i = 2.0 v -- 650 m a i li1 input leakage current port 0, ea 0.45 < v i < v dd - 10 m a i li2 input leakage current p1.6 and p1.7 0 v < v i < 5.5 v 0v < v dd < 5.5 v - 10 m a outputs v ol low level output voltage ports 1, 2 and 3 (except p1.6 and p1.7) i ol = 1.6 ma; notes 6 and 7 - 0.45 v v ol1 low level output voltage port 0, ale, psen i ol = 3.2 ma; notes 4 and 7 - 0.45 v v ol2 low level output voltage p1.6 and p1.7 i ol = 3.0 ma; note 7 - 0.40 v v oh high level output voltage ports 1, 2 and 3 (except p1.6 and p1.7) i oh = - 60 m a; v dd =5v 10% i oh = - 25 m a i oh = - 10 m a 2.4 0.75 v dd 0.9 v dd - - - v
1997 dec 15 54 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 notes to the dc characteristics 1. conditions for: a) the operating supply current is measured with all output pins disconnected; xtal1 driven with t r =t f = 5 ns; v il =v ss +0.5 v; v ih =v dd - 0.5 v; xtal2 not connected; ea = rst = port 0 = p1.6 = p1.7 = v dd ; the wdt is disabled (by the external reset). 2. conditions for: a) the idle mode supply current is measured with all output pins disconnected; xtal1 driven with t r =t f = 5 ns; v il =v ss +0.5 v; v ih =v dd - 0.5 v; xtal2 not connected; the wdt is disabled; ea = rst = v ss ; port 0 = p1.6 = p1.7 = v dd . 3. conditions for: a) the power-down current is measured with all output pins disconnected; xtal2 not connected; wdt is disabled; ea = rst = xtal1 = v ss ; port 0 = p1.6 = p1.7 = v dd . 4. capacitive loading on port 0 and port 2 may cause spurious noise pulses to be superimposed on the low level output voltage of ale, port 1 and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make a high-to-low transition during bus operations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 5. capacitive loading on port 0 and port 2 may cause the high level output voltage on ale and psen to momentarily fall below the 0.9 v dd specification when the address bits are stabilizing. 6. the input threshold voltage of p1.6 and p1.7 (sio1) meets the i 2 c specification, so a voltage below 0.3 v dd will be recognized as a logic 0 while an input above 0.7 v dd will be recognized as a logic 1. 7. under steady state (non-transient) conditions, i ol must be externally limited as follows: a) maximum i ol per port pin:10 ma. b) maximum i ol per 8-bit port:- port 0: 26 ma; ports 1, 2 and 3: 15 ma. c) maximum total i ol for all output pins: 71 ma. if i ol exceeds the test condition, v ol may exceed the related specification. d) pins are not guaranteed to sink current greater than the listed test conditions. 8. i dd max. at other frequencies can be derived from fig.26 where f is the external oscillator frequency in mhz; i dd max. is given in ma. v oh1 high level output voltage port0in in external bus mode, ale, psen, rst i oh = - 800 m a; v dd =5v 10% i oh = - 300 m a; i oh = - 80 m a; note 5 2.4 0.75v dd 0.9v dd - - - v r rst rst pull - down resistor 50 150 k w c i/o i/o pin capacitance test frequency = 1 mhz; t amb =25 c - 10 pf symbol parameter conditions min. max. unit
1997 dec 15 55 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.26 i dd as a function of frequency. valid only within frequency specifications of device under test. handbook, full pagewidth 08 24 40 50 30 10 0 20 mbc478 16 f (mhz) i dd (ma) max active mode typ active mode max idle mode typ idle mode
1997 dec 15 56 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 21 ac characteristics 21.1 ac characteristics 16 mhz version see notes 1, 2 and 3 in section 21.2; cl = 100 pf for port 0, ale and psen; c l = 80 pf for all other outputs unless otherwise speci?ed. symbol parameter 16 mhz variable clock unit min. max. min. max. external program memory t lhll ale pulse duration 85 - 2 t ck - 40 - ns t avll address set-up time to ale 8 - t ck - 55 - ns t llax address hold time after ale 28 - t ck - 35 - ns t lliv time from ale to valid instruction input - 150 - 4 t ck - 100 ns t llpl time from ale to control pulse psen 23 - t ck - 40 - ns t plph control pulse duration psen 143 - 3 t ck - 45 - ns t pliv time from psen to valid instruction input - 83 - 3 t ck - 105 ns t pxix input instruction hold time after psen 0 - 0 - ns t pxiz input instruction ?oat delay after psen - 38 - t ck - 25 ns t aviv address to valid instruction input - 208 - 5 t ck - 105 ns t plaz address ?oat time to psen - 10 - 10 ns external data memory t lhll ale pulse duration 85 - 2 t ck - 40 - ns t avll address set-up time to ale 8 - t ck - 55 - ns t llax address hold time after ale 28 - t ck - 35 - ns t rlrh rd pulse duration 275 - 6 t ck - 100 - ns t wlwh wr pulse duration 275 - 6 t ck - 100 - ns t rldv rd to valid data input - 148 - 5 t ck - 165 ns t rhdx data hold time after rd 0 - 0 - ns t rhdz data ?oat delay after rd - 55 - 2 t ck - 70 ns t lldz time from ale to valid data input - 350 - 8 t ck - 150 ns t avdv address to valid data input - 398 - 9 t ck - 165 ns t llwl time from ale to rd or wr 138 238 3 t ck - 50 3 t ck +50 ns t avwl time from address to rd or wr 120 - 4 t ck - 130 - ns t whlh time from rd or wr high to ale high 23 103 t ck - 40 t ck + 40 ns t qvwx data valid to wr transition 3 - t ck - 60 - ns t qvwh data set-up time before wr 288 - 7 t ck - 150 - ns t whqx data hold time after wr 13 - t ck - 50 - ns t rlaz address ?oat delay after rd - 0 - 0ns
1997 dec 15 57 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 21.2 ac characteristics 24 mhz version see notes 1, 2 and 3.; cl = 100 pf for port 0, ale and psen; c l = 80 pf for all other outputs unless otherwise speci?ed. notes to the ac characteristics 16 and 24 mhz versions 1. for the ac characteristics the following conditions are valid: a) p83c52x ebx : v dd =5 v 10%; v ss =0 v;t amb = 0 to +70 c; t ck min.=63ns b) p83c52x efx: v dd =5v 10%; v ss =0v;t amb = - 40 to +85 c; t ck min. = 63 ns. 2. t ck min. = 1/f max. (maximum operating frequency); t ck = clock period (see section for timing symbol de?nitions). 3. the maximum operating frequency is limited to 16/24 mhz and the minimum to 3.5 mhz (all versions ixx/exx). symbol parameter 24 mhz variable clock unit min. max. min. max. external program memory t lhll ale pulse duration 43 - 2 t ck - 40 - ns t avll address set-up time to ale 17 - t ck - 25 - ns t llax address hold time after ale 17 - t ck - 25 - ns t lliv time from ale to valid instruction input - 102 - 4 t ck - 65 ns t llpl time from ale to control pulse psen 17 - t ck - 25 - ns t plph control pulse duration psen 80 - 3 t ck - 45 - ns t pliv time from psen to valid instruction input - 65 - 3 t ck - 60 ns t pxix input instruction hold time after psen 0 - 0 - ns t pxiz input instruction ?oat delay after psen - 17 - t ck - 25 ns t aviv address to valid instruction input - 128 - 5 t ck - 80 ns t plaz address ?oat time to psen - 10 - 10 ns external data memory t lhll ale pulse duration 43 - 2 t ck - 40 - ns t avll address set-up time to ale 17 - t ck - 25 - ns t llax address hold time after ale 17 - t ck - 25 - ns t rlrh rd pulse duration 150 - 6 t ck - 100 - ns t wlwh wr pulse duration 150 - 6 t ck - 100 - ns t rldv rd to valid data input - 118 - 5 t ck - 90 ns t rhdx data hold time after rd 0 - 0 - ns t rhdz data ?oat delay after rd - 55 - 2 t ck - 28 ns t lldz time from ale to valid data input - 183 - 8 t ck - 150 ns t avdv address to valid data input - 210 - 9 t ck - 165 ns t llwl time from ale to rd or wr 75 175 3 t ck - 50 3 t ck +50 ns t avwl time from address to rd or wr 92 - 4 t ck - 75 - ns t whlh time from rd or wr high to ale high 17 67 t ck - 25 t ck + 25 ns t qvwx data valid to wr transition 12 - t ck - 30 - ns t qvwh data set-up time before wr 162 - 7 t ck - 130 - ns t whqx data hold time after wr 17 - t ck - 25 - ns t rlaz address ?oat delay after rd - 0 - 0ns
1997 dec 15 58 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 22 i 2 c characteristics (bit-level) notes 1. at f clk = 3.5 mhz, this evaluates to 14 286 ns = 4 m s, i.e. the bit-level i 2 c interface can respond to the i 2 c protocol for f clk 3 3.5 mhz. 2. this parameter is determined by the user software, it has to comply with the i 2 c specification. 3. this value gives the auto-clock pulse length which meets the i 2 c specification for the specified xtal1 clock frequency range. alternatively, the scl pulse may be timed by software. 4. spikes on sda and scl lines with a duration of less than 4 f clk will be filtered out. 5. the rise time is determined by the external bus line capacitance and pull-up resistor, it must be 1 m s. 6. the maximum capacitance on bus lines sda and scl is 400 pf. symbol parameter input output i 2 c spec unit scl timing t hd;sta start condition hold time 3 14 t ck ; note 1 note 2 3 4.0 m s t low scl low time 3 16 t ck note 2 3 4.7 m s t high scl high time 3 14 t ck ; note 1 3 80 t ck ; note 3 3 4.0 m s t rc scl rise time 1; note 4 note 5 1.0 m s t fc scl fall time 0.3; note 4 0.3; note 6 0.3 m s sda timing t su;dat data set-up time 3 250 ns note 2 3 250 ns t hd;dat data hold time 3 0 ns note 2 3 0ns t su;sta repeated start set-up time 3 14 t ck ; note 1 note 2 3 4.7 m s t su;sto stop condition set - up time 3 14 t ck ; note 1 note 2 3 4.0 m s t buf bus free time 3 14 t ck ; note 1 note 2 3 4.7 m s t rd sda rise time 1; note 4 note 5 1.0 m s t fd sda fall time 300 ns; note 4 0.3; note 6 0.3 m s
1997 dec 15 59 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 23 xtal1 characteristics oscillator circuitry: crystal capacitors: c1 = c2 = 20 pf (see fig.31). table 36 external clock drive xtal 24 serial port characteristics see table 37 and fig.32. table 37 serial port timing: shift register mode v dd =5 v 10%; v ss =0 v;t amb =0 c to 70 c; load capacitance = 80 pf symbol parameter variable clock unit min. max. f clk clock frequency 3.5 24 mhz t ck clock period 42 286 ns t high high time 17 t ck - t low ns t low low time 17 t ck - t high ns t r rise time - 5ns t f fall time - 5ns t cy cycle time (t cy = 12 t ck ) 0.5 3.43 m s symbol parameter 24 mhz oscillator variable oscillator unit min. max. min. max. t xlxl serial port clock cycle time 0.5 - 12 t ck -m s t qvxh output data setup to clock rising edge 283 - 10 t ck - 133 - ns t xhqx output data hold after clock rising edge 23 - 2 t ck - 60 - ns t xhdx input data hold after clock rising edge 0 - 0 - ns t xhdv clock rising edge to input data valid - 283 - 10 t ck - 133 ns
1997 dec 15 60 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 25 timing diagrams handbook, full pagewidth t rd t fd t rc t fc t hd;sta t low t high t su;dat1 t hd;dat t su;dat2 t su;dat3 0.7 v dd 0.3 v dd t su;sto t buf t su;sta sda (input / output) scl (input / output) start condition repeated start condition stop condition start or repeated start condition 0.7 v dd 0.3 v dd mbc482 fig.27 i 2 c interface timing.
1997 dec 15 61 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.28 external program memory read cycle. handbook, full pagewidth mbc483 - 1 t lhll t avll t llpl t plph t lliv t pliv t llax t plaz t pxix t pxiz instr in a0 - a7 a0 - a7 a8 - a15 a8 - a15 ale psen port 0 port 2 t aviv
1997 dec 15 62 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mbc485 - 1 ale psen port 0 port 2 rd t avwl t avll t llax t llwl t rlrh rhdx t t whlh a0 - a7 from ri or dpl data in a0 - a7 from pcl instr in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph rhdz t t avdv rldv t t lldv fig.29 external data memory read cycle.
1997 dec 15 63 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mbc486 - 1 ale psen port 0 port 2 wr t avwl t avll t llax qvwx t t llwl t wlwh whqx t t whlh a0 - a7 from ri or dpl data out a0 - a7 from pcl instr in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph t qvwh fig.30 external data memory write cycle.
1997 dec 15 64 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 handbook, full pagewidth mbc480 2.0 v 0.8 v 2.4 v 0.45 v 2.0 v 0.8 v 2.4 v 0.45 v float (b) (a) 2.4 v 0.45 v 2.0 v 0.8 v 2.0 v 0.8 v test points fig.31 ac testing input, output waveform (a) and float waveform (b). ac testing inputs are driven at 2.4 v for a logic 1 and 0.45 v for a logic 0. timing measurements are taken at 2.0 v for a logic 1 and 0.8 v for logic 0 see (a). the float state is defined as the point at which a port 0 pin sinks 3.2 ma or sources 400 m a at the voltage test levels see (b). fig.32 external clock drive xtal1. see table 36. handbook, full pagewidth mbc479 t high t low t ck t r t f v ih1 v ih1 0.8 v 0.8 v v ih1 v ih1 0.8 v 0.8 v
1997 dec 15 65 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.33 shift register mode timing waveforms. see table 37. h andbook, full pagewidth mbc475 instruction ale clock 8 7 6 5 4 3 2 1 0 valid write to sbuf output data clear ri input data t xlxl t xhqx t qvxh t xhdv t xhdx set ri set ti valid valid valid valid valid valid valid
1997 dec 15 66 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 fig.34 instruction cycle timing. a ndbook, full pagewidth mbc487 - 1 p1 p2 s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 p1 p2 s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 one machine cycle one machine cycle xtal1 input address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 inst. in address a8 - a15 address a8 - a15 address a8 - a15 address a8 - a15 address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 data output or data input address a8 - a15 address a8 - a15 or port 2 out address a8 - a15 old data new data sampling time of i/o port pins during input (including int0 and int1) serial port clock port input port output port 2 bus (port 0) read or write of external data memory port 2 bus (port 0) external program memory fetch wr rd only active during a write to external data memory only active during a read from external data memory psen ale dotted lines are valid when rd or wr are active
1997 dec 15 67 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 25.1 timing symbol de?nitions oscillator: f clk = clock frequency t ck = clock period timing symbols (acronyms): each timing symbol has five characters. the first character is always a 't' (= time). the remaining four characters of the symbol (typed in subscript), depending on their relative positions, indicate the name of a signal or the logical status of that signal. the designations are as follows: a =address c = clock d = input data h = logic level high i = instruction (program memory contents) l = logic level low or ale p= psen q = output data r= rd signal t = time v = valid w= wr signal x = no longer a valid logic level z = float examples: t avll = time for address valid to ale low t llpl = time for ale low to psen low
1997 dec 15 68 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 26 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot129-1 92-11-17 95-01-14 a min. a max. b z max. w m e e 1 1.70 1.14 0.53 0.38 0.36 0.23 52.50 51.50 14.1 13.7 3.60 3.05 0.254 2.54 15.24 15.80 15.24 17.42 15.90 2.25 4.7 0.51 4.0 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.12 0.01 0.10 0.60 0.62 0.60 0.69 0.63 0.089 0.19 0.020 0.16 051g08 mo-015aj m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 40 1 21 20 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
1997 dec 15 69 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 unit a a min. max. max. max. max. 1 a 4 b p e (1) (1) (1) eh e z y w v b references outline version european projection issue date iec jedec eiaj mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 0.51 2.16 45 o 0.18 0.10 0.18 dimensions (millimetre dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. sot187-2 d (1) 16.66 16.51 h d 17.65 17.40 e z 2.16 d b 1 0.81 0.66 k 1.22 1.07 k 1 0.180 0.165 0.020 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.020 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e e e d 16.00 14.99 0.630 0.590 16.00 14.99 0.630 0.590 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k 1 k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 mo-047ac 0 5 10 mm scale 92-11-17 95-02-25 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e
1997 dec 15 70 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 0.85 0.75 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 92-11-17 95-02-04 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p q detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1997 dec 15 71 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 27 soldering 27.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 27.2 dip 27.2.1 s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 27.2.2 r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 27.3 plcc and qfp 27.3.1 r eflow soldering reflow soldering techniques are suitable for all plcc and qfp packages. the choice of heating method may be influenced by larger plcc or qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. 27.3.2 w ave soldering 27.3.2.1 plcc wave soldering techniques can be used for all plcc packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream corners. 27.3.2.2 qfp wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm.
1997 dec 15 72 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 27.3.2.3 method (plcc and qfp) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 27.3.3 r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 28 definitions 29 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 30 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 dec 15 73 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 notes
1997 dec 15 74 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 notes
1997 dec 15 75 philips semiconductors product speci?cation 8-bit microcontrollers p83c524; p80c528; p83c528 notes
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